1. Field of the Invention
This specification relates to a system controller for controlling a cache device configuring a multiprocessor system and a cache control method for controlling the cache device, and may be applied to a system controller and a cache control method capable of reducing state modify requests to a data block on a cache device of another system and improving the access performance of a cache device of a related cache device.
2. Description of the Related Art
Conventionally, with an increasing number of requests for a higher speed computer system, a multiprocessor system is provided with a cache device for each CPU. The data on the cache device provided for each CPU is managed for each block on the cache device according to the rules for maintaining the consistency of data with the cache memory referred to as a cache coherence protocol to assure the correctness of data between cache devices, that is, to share data and maintain the consistency.
An MESI cache protocol for managing four states of “M”, “E”, “S”, and “I” is well known as a conventional common cache protocol. “M” indicates a modified state in which valid data is held in only one of a plurality of cache devices, the data is modified, and it is not guaranteed that the value of the data is the same as the value in the main storage. “E” indicates an exclusive state in which valid data is held in only one of a plurality of cache devices. “S” indicates a shared state in which same data is held in a plurality of cache devices. “I” indicates an invalid state in which data on a cache device is invalid.
In the cache control using the above-mentioned MESI cache protocol, when a fetch request in which a CPU stores a data block in a cache device and another CPU refers to the data block is issued, a write of the data block to the main storage (hereinafter referred to as an MS write) is required, thereby taking longer accessing time.
Thus, the necessity of the MS write when a fetching process is performed is eliminated by adding a shared modified state O to the MESI cache protocol. The symbol “O” indicates an owner.
However, in the cache protocol having the above-mentioned five states, when a fetching process in the related system is followed by a storing process in another system, a state modify request to switch to an invalid state I is required for the other system in the shared modified state O. In this case, the state modify request to the other system requires a longer time to perform the storing process. Since the storing process is frequently performed in the related system on the data block on the cache obtained by the fetch request of the related system, thereby largely affecting the accessibility on the entire device.
Therefore, in the cache device having cache memory and a cache controller, the cache memory holds a part of data in the main storage for each block of a cache line, and also holds information about the state of the data block held in the cache line while the cache controller represents the state of the data block in six states of, for example, the invalid state I, the shared state S, the exclusive state E, the modified state M, the shared modified state O, and the writable modified state W for stepwise sharing when a fetch request is issued, thereby controlling the cache memory.
In this technique, the state of the data block to be managed on the cache device is classified, thereby reducing the number of state modify requests to another system and speeding up the access to the cache device.
However, in the above-mentioned snoop control, since there can be many cases in which the state of an object data block cannot be discriminated by a copy (hereinafter referred to as a TAG2) of a tag (TAG) of a cache memory device provided for the system controller, an error can occur in transferring a data block between cache devices.
For example, when fetch access is executed, the state at the entry in the cache memory of a requesting CPU depends on the state (exclusive state E, writable modified state W, modified state M) of a hit data block, but the discrimination cannot be performed using a tag table of the system controller. Therefore, it is necessary to know the entry state of the object data block from the hit cache memory. The system controller normally updates the tag tables of all relevant cache memory after a snooping process is completed and a data transfer request to the hit cache memory or an issue of a memory access request to the main memory is determined. However, since the state of the object data block is not determined until a reply to the data transfer request from the cache memory is received, there can be a period in which the state on the tag table is uncertain.